The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS.
The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra- low power applications. CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. WSN nodes have been designed using JN5121-Z01-M01 module produced by jennic company and IEEE 802.15.4/ZigBee technology. Consequently, it is of great importance to decrease the size of a node, reduce its power consumption and extend its life in network. Power consumption and size are the most important consideration when nodes are designed for distributed WSN (wireless sensor networks). It is of great value to use it where human is quite difficult to reach. Xu, Jun You, Bo Cui, Juan Ma, Jing Li, Xin Sensor network integrates sensor technology, MEMS (Micro-Electro-Mechanical system) technology, embedded computing, wireless communication technology and distributed information management technology. The experimental results show that energy consumption of a three-level cache hierarchy can be saved from 5.29% up to 27.94% compared with other key approaches while the performance of the multi-core system even has a slight improvement counting in hardware overhead. The BACH was implemented on the GEM5 simulator. The equivalent gate count of the core area without memory is approximately 50 k.
The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35InlineEquation not available: see fulltext.m SPQM and 0.25InlineEquation not available: see fulltext.m 1P5M library. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. Tsao, Ya-Lan Chen, Wei-Hao Tan, Ming Hsuan Lin, Maw-Ching Jou, Shyh-Jye This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility.